US 12,460,950 B2
System on a chip with always-on processor
Brijesh Tripathi, Los Altos, CA (US); Shane J. Keil, San Jose, CA (US); Manu Gulati, Saratoga, CA (US); Jung Wook Cho, Cupertino, CA (US); Erik P. Machnicki, San Jose, CA (US); Gilbert H. Herbeck, Livermore, CA (US); Timothy J. Millet, Mountain View, CA (US); Joshua P. de Cesare, Campbell, CA (US); and Anand Dalal, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 12, 2021, as Appl. No. 17/372,764.
Application 17/372,764 is a continuation of application No. 16/689,555, filed on Nov. 20, 2019, granted, now 11,079,261.
Application 16/689,555 is a continuation of application No. 16/019,087, filed on Jun. 26, 2018, granted, now 10,488,230, issued on Nov. 26, 2019.
Application 16/019,087 is a continuation of application No. 14/458,885, filed on Aug. 13, 2014, granted, now 10,031,000, issued on Jul. 24, 2018.
Claims priority of provisional application 62/004,317, filed on May 29, 2014.
Prior Publication US 2021/0341317 A1, Nov. 4, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G01D 9/00 (2006.01); A61G 3/06 (2006.01); B60P 1/43 (2006.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 1/3293 (2019.01); G06F 13/16 (2006.01)
CPC G01D 9/00 (2013.01) [A61G 3/061 (2013.01); B60P 1/433 (2013.01); G06F 1/3206 (2013.01); G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G06F 13/1689 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of components, wherein the plurality of components includes at least one central processing unit (CPU) processor and a memory controller configured to control a first memory; and
a first component coupled to the plurality of components, wherein:
the first component comprises a second memory;
the first component is configured to remain powered on while the plurality of components are powered off;
the first component is configured to capture a plurality of samples of sensor data from at least one sensor in a system that includes the integrated circuit, and the first component is configured to write the plurality of samples to the second memory;
the first component is configured to search the plurality of samples in the second memory for a predetermined pattern;
the first component is configured to cause the memory controller and a communication path to the memory controller from the first component to be powered on while the CPU processor remains powered off in response to the captured plurality of samples filling to a threshold level in the second memory and the first component detecting a lack of the predetermined pattern in the captured plurality of samples; and
the first component is configured to transfer the captured plurality of samples from the second memory to the first memory while the CPU processor remains powered off.