US 12,460,315 B2
Method for manufacturing semiconductor substrates and method for suppressing introduction of displacement to growth layer
Tadaaki Kaneko, Sanda (JP); and Daichi Dojima, Sanda (JP)
Assigned to KWANSEI GAKUIN EDUCATIONAL FOUNDATION, Hyogo (JP); and TOYOTA TSUSHO CORPORATION, Aichi (JP)
Appl. No. 17/919,194
Filed by KWANSEI GAKUIN EDUCATIONAL FOUNDATION, Hyogo (JP); and TOYOTA TSUSHO CORPORATION, Aichi (JP)
PCT Filed Mar. 30, 2021, PCT No. PCT/JP2021/013750
§ 371(c)(1), (2) Date Oct. 14, 2022,
PCT Pub. No. WO2021/210397, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 2020-072554 (JP), filed on Apr. 14, 2020.
Prior Publication US 2023/0160100 A1, May 25, 2023
Int. Cl. C30B 23/04 (2006.01); C30B 29/40 (2006.01)
CPC C30B 23/04 (2013.01) [C30B 29/403 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor substrate, the method comprising: a processing step of removing a part of an underlying substrate to form a pattern with a minor angle; and a crystal growth step of forming a growth layer on the underlying substrate on which the pattern is formed.