US 12,133,470 B2
Semiconductor structure and method of forming the same
Harry-Hak-Lay Chuang, Zhubei (SG); Kuei-Hung Shen, Hsinchu (TW); Chern-Yow Hsu, Hsin-Chu County (TW); and Shih-Chang Liu, Kaohsiung County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CPMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu (TW)
Filed on Nov. 28, 2022, as Appl. No. 18/059,073.
Application 18/059,073 is a division of application No. 16/931,632, filed on Jul. 17, 2020, granted, now 11,515,473.
Application 16/048,247 is a division of application No. 15/159,669, filed on May 19, 2016, granted, now 10,270,025, issued on Apr. 23, 2019.
Application 16/931,632 is a continuation of application No. 16/048,247, filed on Jul. 28, 2018, granted, now 10,720,571, issued on Jul. 21, 2020.
Claims priority of provisional application 62/273,469, filed on Dec. 31, 2015.
Prior Publication US 2023/0088093 A1, Mar. 23, 2023
Int. Cl. H10N 50/10 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/10 (2023.02) [H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of semiconductor device fabrication, comprising:
providing a substrate having an Nth metal layer with a first portion in a memory region and a second portion in a logic region;
forming a bottom portion of a bottom electrode interfacing the first portion of the Nth metal layer;
depositing a conductive material over the bottom portion of the bottom electrode, wherein the conductive material is deposited on the memory region and the logic region;
forming a magnetic tunneling junction (MTJ) structure over the conductive material in the memory region;
depositing a dielectric layer over the MTJ structure, wherein the dielectric layer extends over the logic region;
etching the dielectric layer to form spacers on sidewalls of the MTJ structure, wherein the etching removes the dielectric layer from the logic region; and
while using the spacers as a masking element, etching the conductive material to form a top portion of the bottom electrode in the memory region and remove the conductive material from the logic region.