US 12,133,419 B2
Display device, method of manufacturing the same, and electronic apparatus
Seiichiro Jinta, Kanagawa (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Dec. 8, 2022, as Appl. No. 18/077,639.
Application 18/077,639 is a continuation of application No. 17/567,426, filed on Jan. 3, 2022, granted, now 11,569,325.
Application 17/567,426 is a continuation of application No. 17/235,326, filed on Apr. 20, 2021, granted, now 11,233,109, issued on Jan. 25, 2022.
Application 17/235,326 is a continuation of application No. 16/813,361, filed on Mar. 9, 2020, granted, now 11,004,924.
Application 16/813,361 is a continuation of application No. 16/369,162, filed on Mar. 29, 2019, granted, now 10,615,238.
Application 16/369,162 is a continuation of application No. 16/296,612, filed on Mar. 8, 2019, granted, now 10,615,237, issued on Apr. 7, 2020.
Application 16/296,612 is a continuation of application No. 16/181,838, filed on Nov. 6, 2018, granted, now 10,312,314, issued on Jun. 4, 2019.
Application 16/181,838 is a continuation of application No. 16/014,753, filed on Jun. 21, 2018, granted, now 10,147,779, issued on Dec. 4, 2018.
Application 16/014,753 is a continuation of application No. 15/965,153, filed on Apr. 27, 2018, granted, now 10,121,841, issued on Nov. 6, 2018.
Application 15/965,153 is a continuation of application No. 15/813,983, filed on Nov. 15, 2017, granted, now 10,026,796, issued on Jul. 17, 2018.
Application 15/813,983 is a continuation of application No. 14/909,586, granted, now 10,103,212, issued on Oct. 16, 2018, previously published as PCT/JP2014/068876, filed on Jul. 16, 2014.
Claims priority of application No. 2013-189836 (JP), filed on Sep. 12, 2013; and application No. 2014-021604 (JP), filed on Feb. 6, 2014.
Prior Publication US 2023/0363204 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10K 50/12 (2023.01); G09G 3/20 (2006.01); G09G 3/3233 (2016.01); H01L 27/12 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H10K 50/13 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/35 (2023.01); H10K 59/12 (2023.01); H10K 59/38 (2023.01); H10K 102/00 (2023.01)
CPC H10K 59/1213 (2023.02) [G09G 3/2003 (2013.01); G09G 3/3233 (2013.01); H01L 27/1222 (2013.01); H01L 27/1229 (2013.01); H01L 27/1237 (2013.01); H01L 27/1251 (2013.01); H01L 27/127 (2013.01); H01L 29/495 (2013.01); H01L 29/78648 (2013.01); H01L 29/78678 (2013.01); H01L 29/78696 (2013.01); H10K 50/13 (2023.02); H10K 59/131 (2023.02); H10K 59/351 (2023.02); G09G 2230/00 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/08 (2013.01); G09G 2320/02 (2013.01); H01L 29/78672 (2013.01); H10K 59/1201 (2023.02); H10K 59/38 (2023.02); H10K 2102/3026 (2023.02)] 34 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
an electrically-conductive layer arranged on the substrate, the electrically-conductive layer, in a plan view, including a first region, a second region, and a third region;
a first insulating layer arranged on the electrically-conductive layer;
a second insulating layer that is distinct from the first insulating layer;
a first silicon layer;
a second silicon layer that is distinct from the first silicon layer;
a plurality of pixels, at least one pixel of the plurality of pixels including:
a light emitting element;
a capacitor configured to store a voltage;
a drive transistor including a first channel, a first gate electrode, a coupling section, and a plurality of channel sections coupled in series through the coupling section, wherein the drive transistor is configured to supply a drive current to the light emitting element; and
a write transistor including a second channel, the write transistor configured to supply a pixel voltage supplied from a data line to the capacitor, the second channel is a part of the second silicon layer,
wherein the second insulating layer is arranged on the first channel,
wherein the first region includes the first gate electrode,
wherein the second region includes a first contact of the drive transistor, and
wherein the third region includes the first channel.