US 12,133,389 B2
Semiconductor memory device including pass transistors with variable sizes
Sung Wook Jung, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 18, 2022, as Appl. No. 17/723,167.
Application 17/723,167 is a continuation in part of application No. 16/944,032, filed on Jul. 30, 2020, granted, now 11,309,027.
Claims priority of application No. 10-2020-0047216 (KR), filed on Apr. 20, 2020.
Prior Publication US 2022/0238544 A1, Jul. 28, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/28 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/40 (2023.02) [G11C 16/04 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/28 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including at least one memory block, the memory block including at least one source selection line, a plurality of word lines, at least one drain selection line, and at least one dummy word line, which are stacked, and
a pass transistor (TR) unit including: at least one source pass transistor configured to selectively transmit a source driving signal to the source selection line, a plurality of memory pass transistors configured to selectively transmit a word line driving signal to the plurality of word lines, respectively, at least one drain pass transistor configured to selectively transmit a drain driving signal to the drain selection line, and at least one dummy pass transistor configured to selectively transmit a dummy word line driving signal to the at least one dummy word line,
wherein the source driving signal, the word line driving signal, the drain driving signal, and the dummy word line driving signal are each associated with a respective voltage range, and
wherein sizes of the source pass transistor, the plurality of memory pass transistors, the drain pass transistor, and the at least one dummy pass transistor are set based on the respective voltage ranges.