CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 14 Claims |
1. A memory device, comprising:
a layer stack including a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer;
an alternating stack of insulating layers and electrically conductive layers located over the layer stack; and
a memory opening fill structure vertically extending through the alternating stack, the upper source-level semiconductor layer, the source contact layer, and an upper portion of the lower source-level semiconductor layer,
wherein the memory opening fill structure comprises:
a vertical semiconductor channel vertically extending through the alternating stack and into the upper portion of the lower source-level semiconductor layer;
a memory film laterally surrounding the vertical semiconductor channel and vertically extending through the alternating stack and into an upper portion of the upper source-level semiconductor layer; and
a first annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer.
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