| CPC H10B 41/27 (2023.02) [G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 3 Claims |
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1. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming support pillar structures through the alternating stack;
forming stepped surfaces by patterning the alternating stack and the support pillar structures, wherein the stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack in a staircase region;
forming a retro-stepped dielectric material portion over the stepped surfaces;
forming memory openings through the alternating stack in a memory array region;
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a vertical stack of memory elements;
forming electrically conductive layers by replacing at least the sacrificial material layers with at least one electrically conductive material; and
forming contact via structures through the retro-stepped dielectric material portion in contact with the electrically conductive layers,
wherein a first support pillar structure of the support pillar structures is located directly below a first contact via structure of the contact via structures; and
wherein the first contact via structure has a bottom surface that is located entirely inside and is laterally offset inward from a periphery of a topmost surface of the first support pillar structure in a plan view along a vertical direction.
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