US 12,133,379 B2
Semiconductor memory device and manufacturing method of semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 20, 2021, as Appl. No. 17/235,577.
Claims priority of application No. 10-2020-0134645 (KR), filed on Oct. 16, 2020.
Prior Publication US 2022/0123005 A1, Apr. 21, 2022
Int. Cl. H10B 41/27 (2023.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 19 Claims
OG exemplary drawing
 
11. A semiconductor memory device comprising:
a first channel structure and a second channel structure, extending in parallel to each other;
a tunnel insulating layer surrounding a sidewall of each of the first channel structure and the second channel structure;
a data storage layer surrounding the sidewall of each of the first channel structure and the second channel structure with the tunnel insulating layer interposed between the data storage layer and the sidewall of each of the first channel structure and the second channel structure;
a blocking insulating layer surrounding the sidewall of each of the first channel structure and the second channel structure with the data storage layer and the tunnel insulating layer, which are interposed between the blocking insulating layer and the sidewall of each of the first channel structure and the second channel structure;
a first lower select line surrounding the first channel structure with the blocking insulating layer, the data storage layer, and the tunnel insulating layer, which are interposed between the first lower select line and the first channel structure;
a second lower select line surrounding the second channel structure with the blocking insulating layer, the data storage layer, and the tunnel insulating layer, which are interposed between the second lower select line and the second channel structure;
an isolation layer disposed between the first lower select line and the second lower select line;
a first upper select line surrounding the first channel structure with the tunnel insulating layer interposed between the first upper select line and the first channel structure, the first upper select line being disposed on the first lower select line;
a second upper select line surrounding the second channel structure with the tunnel insulating layer interposed between the second upper select line and the second channel structure, the second upper select line being disposed on the second lower select line; and
interlayer insulating layers and word lines, alternately stacked between the first lower select line and the first upper select line, wherein the interlayer insulating layers and the word lines extend between the second lower select line and the second upper select line,
wherein the tunnel insulating layer surrounding the first channel structure is in contact with the first upper select line, and
wherein the tunnel insulating layer surrounding the second channel structure is in contact with the second upper select line.