US 12,133,330 B2
Wiring substrate and semiconductor device
Akihiro Takeuchi, Nagano (JP)
Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed by SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed on Oct. 18, 2022, as Appl. No. 18/047,348.
Claims priority of application No. 2021-174579 (JP), filed on Oct. 26, 2021.
Prior Publication US 2023/0130183 A1, Apr. 27, 2023
Int. Cl. H05K 1/11 (2006.01); H05K 1/09 (2006.01); H05K 1/18 (2006.01)
CPC H05K 1/113 (2013.01) [H05K 1/09 (2013.01); H05K 1/181 (2013.01); H05K 2201/0376 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09736 (2013.01); H05K 2201/10674 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A wiring substrate comprising: an insulating layer; a pad in a via hole piercing through the insulating layer, the pad being exposed at a first surface of the insulating layer; a via conductor on the pad in the via hole; and a wiring part on a second surface of the insulating layer facing away from the first surface, the wiring part being connected to the pad through the via conductor in the via hole, wherein a diameter of the pad, a diameter of the via conductor, and a diameter of the via hole are equal to one another at an interface between the pad and the via conductor.