US 12,133,008 B2
Solid-state imaging element and imaging device
Satoshi Azuhata, Tokyo (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/798,460
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jan. 26, 2021, PCT No. PCT/JP2021/002567
§ 371(c)(1), (2) Date Aug. 9, 2022,
PCT Pub. No. WO2021/192576, PCT Pub. Date Sep. 30, 2021.
Claims priority of application No. 2020-050475 (JP), filed on Mar. 23, 2020.
Prior Publication US 2023/0049629 A1, Feb. 16, 2023
Int. Cl. H04N 25/75 (2023.01); H04N 25/768 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01)
CPC H04N 25/75 (2023.01) [H04N 25/768 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/79 (2023.01)] 14 Claims
OG exemplary drawing
 
1. A solid-state imaging element comprising:
a differential amplifier circuit that amplifies a difference between potentials of a pair of input nodes and outputs the difference from an output node;
a transfer transistor that transfers charge from a photoelectric conversion element to a floating diffusion layer;
an auto-zero transistor that short-circuits the floating diffusion layer and the output node in a predetermined period; and
a source follower circuit that supplies a potential to one of the pair of input nodes according to a potential of the floating diffusion layer, wherein
the differential amplifier circuit includes:
first and second differential transistors; and
a first current source transistor that is commonly connected to sources of the first and second differential transistors and that supplies a first predetermined current, wherein
a predetermined reference signal is inputted to a gate of the first differential transistor, and
the potential from the source follower circuit is inputted to a gate of the second differential transistor.