US 12,132,825 B2
Technologies for accelerated hierarchical key caching in edge systems
Timothy Verrall, Pleasant Hill, CA (US); Thomas Willhalm, Sandhausen (DE); Francesc Guim Bernat, Barcelona (ES); Karthik Kumar, Chandler, AZ (US); Ned M. Smith, Beaverton, OR (US); Rajesh Poornachandran, Portland, OR (US); Kapil Sood, Portland, OR (US); Tarun Viswanathan, El Dorado Hills, CA (US); John J. Browne, Limerick (IE); and Patrick Kutch, Tigard, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,558.
Application 17/561,558 is a continuation of application No. 16/368,982, filed on Mar. 29, 2019, granted, now 11,212,085.
Prior Publication US 2022/0200788 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/08 (2006.01)
CPC H04L 9/083 (2013.01) [H04L 9/0836 (2013.01); H04L 9/0891 (2013.01); H04L 9/0894 (2013.01); H04L 9/0897 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A first edge appliance device comprising:
interface circuitry to receive a first request for a key, the first request from an edge device or a second edge appliance device;
instructions in the first edge appliance device; and
processor circuitry to be programmed by the instructions to:
determine the key is not in a key cache of the first edge appliance device;
cause transmission of a second request for the key to a third edge appliance device; and
add the key to the key cache.