CPC H04L 7/033 (2013.01) [H03K 5/26 (2013.01)] | 20 Claims |
7. An electronic device, comprising:
a reference clock node configured to provide a reference clock signal having a reference period, the reference clock signal having a first logic value during a first subperiod of the reference period and having a second logic value during a second subperiod of the reference period;
a sampling clock node configured to receive a sampling clock signal having a sampling clock period, wherein the sampling clock period is shorter than the reference period of the reference clock signal;
a measuring circuit block configured to:
measure the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal; and
measure the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal;
a detecting circuit block configured to detect a starting edge of a first clock signal having a first clock period greater than the reference period;
a reconstructing circuit block configured to produce a reconstructed reference signal based on the measured first and second number of periods of the sampling clock signal and on the detected starting edge; and
a comparator circuit block configured to:
perform a comparison of the first clock period of the first clock signal with a period of the reconstructed reference signal, obtaining, as a result of the comparison, a differential signal indicative of a difference therebetween; and
provide the differential signal to user circuitry to calibrate the first clock signal based on the differential signal.
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