CPC H04L 69/08 (2013.01) [H04L 1/0041 (2013.01); H04L 1/0061 (2013.01); H04L 1/007 (2013.01); H04L 1/0072 (2013.01); H04L 1/0083 (2013.01); H04L 69/02 (2013.01); H04L 69/18 (2013.01); H04L 69/22 (2013.01); H04L 69/324 (2013.01); H04L 1/0003 (2013.01)] | 18 Claims |
7. A system comprising:
one or more processors; and
a memory communicably coupled to the one or more processors and including instructions that when executed by the one or more processors cause the one or more processors to:
generate a packet comprising a plurality of flits having different formats according to different communication protocols, the packet including a link-level flit having a first format according to a first communications protocol supporting link-level retry and a plurality of end-to-end flits having a second format according to a second communications protocol supporting end-to-end retry, wherein the link-level flit is a header flit identifying the beginning of the contiguous burst of flits, and the packet further comprises:
a second link-level flit having a third format according to a third communications protocol and formatted as a tail flit to identify the end of the contiguous burst; and
transmit the plurality of flits over a communications channel from the transmitter to the receiver in a contiguous burst, the contiguous burst transmitting each of the plurality of flits that define the packet in non-interleaved succession.
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