US 12,132,590 B2
Hardware-efficient PAM-3 encoder and decoder
Sunil Sudhakaran, Brisbane, CA (US)
Assigned to NVIDIA, Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Sep. 9, 2022, as Appl. No. 17/931,062.
Claims priority of provisional application 63/330,315, filed on Apr. 13, 2022.
Claims priority of provisional application 63/329,838, filed on Apr. 11, 2022.
Claims priority of provisional application 63/328,172, filed on Apr. 6, 2022.
Claims priority of provisional application 63/321,534, filed on Mar. 18, 2022.
Prior Publication US 2023/0327924 A1, Oct. 12, 2023
Int. Cl. H04L 25/49 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01); H04L 1/00 (2006.01)
CPC H04L 25/4917 (2013.01) [H03M 13/1111 (2013.01); H03M 13/611 (2013.01); H04L 1/0061 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits, the transceiver comprising:
a plurality of communication channels comprising a plurality of data channels, a plurality of auxiliary data channels, and an error correction channel;
an encoder configured to:
apply 11b7s encoding to at least some of the data bits to generate first PAM-3 symbols on each of the plurality of communication channels; and
apply 11b7s encoding to a combination of 3 of the data bits and 8 bits of a cyclic redundancy check (CRC) value comprised by the meta-data bits to generate a first set of 7 PAM-3 symbols on the error correction channel.