| CPC H03M 13/19 (2013.01) [G06F 11/10 (2013.01); G06F 11/1012 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G11C 8/08 (2013.01); G11C 11/4085 (2013.01); G11C 11/4096 (2013.01); G11C 29/52 (2013.01); H03M 13/611 (2013.01); G11C 5/04 (2013.01)] | 19 Claims |
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1. A memory system, comprising:
a memory module including a first memory device, a second memory device, a third memory device, and a fourth memory device, and a first error correction code (ECC) device; and
a memory controller configured to exchange first user data with each of the first memory device, the second memory device, the third memory device, and the fourth memory device through 8 data lines and to exchange first ECC data with the first ECC device of the memory module through 4 data lines,
wherein the memory controller includes an ECC engine configured to detect and correct a 32-random bit error of the first user data based on the first ECC data,
wherein the first ECC data include first detection data and first correction data,
wherein the ECC engine of the memory controller is configured to generate the first detection data and the first correction data by performing an ECC operation on the first user data in units of 32 bits and to generate second detection data based on the first user data read from the memory module, and
wherein, when the second detection data are different from the first detection data read from the memory module, the ECC engine of the memory controller is configured to perform correction of the 32-random bit error of the first user data based on the first correction data read from the memory module.
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