US 12,132,386 B2
Integrated circuit with low power mode management
Venkateswar Kowkutla, Allen, TX (US); Kazunobu Shin, Plano, TX (US); Venkateswara Pothireddy, Mckinney, TX (US); Siva Kothamasu, Frisco, TX (US); John Apostol, Richardson, TX (US); Raghavendra Santhanagopal, Mckinney, TX (US); Rajagopal Kollengode Ananthanarayanan, Plano, TX (US); Rejitha Nair, Southlake, TX (US); Charles Gerlach, Dallas, TX (US); and Ravi Teja Reddy, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jan. 27, 2023, as Appl. No. 18/160,308.
Claims priority of provisional application 63/303,548, filed on Jan. 27, 2022.
Prior Publication US 2023/0238872 A1, Jul. 27, 2023
Int. Cl. H02M 3/04 (2006.01); H02M 1/00 (2006.01)
CPC H02M 1/0032 (2021.05) [H02M 3/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a first control block including an output, the first control block configured to provide a first low power mode (LPM) control signal that indicates a first LPM;
a second control block including a first output and a second output, the second control block configured to provide, at the first output, a second LPM control signal that indicates a second LPM that is different from the first LPM;
a multiplexer including a first input, a second input, a control input, and an output, the first input of the multiplexer coupled to the output of the first control block, the second input of the multiplexer coupled to the first output of the second control block, and the control input coupled to the second output of the second control block; and
an input/output (IO) block including an input and a physical connector adapted to be coupled to a device external to the IC, the input of the IO block coupled to the output of the multiplexer, and the IO block configured to provide a signal at the physical connector in response to the input of the IO block.