| CPC H01L 29/78696 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/0259 (2013.01); H01L 29/0665 (2013.01); H01L 29/167 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a plurality of channel layers vertically spaced apart from each other on the active region, and including a semiconductor material;
a gate structure extending in a second direction on the substrate,
wherein the gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers; and
a source/drain region disposed on the active region on at least one side of the gate structure,
wherein the source/drain region contacts the plurality of channel layers and includes first impurities,
wherein in a channel layer of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration,
wherein the channel layer of the plurality of channel layers is disposed between two adjacent gate layers of the gate structure.
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