US 12,132,118 B2
Semiconductor device having a multilayer source/drain region and methods of manufacture
Wei-Min Liu, Hsinchu (TW); Li-Li Su, Chubei (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 15, 2021, as Appl. No. 17/231,183.
Prior Publication US 2022/0336677 A1, Oct. 20, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/0665 (2013.01); H01L 29/66742 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
forming an opening through a multilayer stack and into a substrate, the multilayer stack comprising alternating sacrificial layers and semiconductor layers, the opening exposing sidewalls of the sacrificial layers and the semiconductor layers;
depositing a first semiconductor material in the opening, wherein depositing the first semiconductor material comprises depositing a first portion along a bottom of the opening and a second portion on the sidewalls of the semiconductor layers, wherein the first semiconductor material and the semiconductor layers have a same conductivity type;
removing at least a portion of the second portion of the first semiconductor material;
forming a second semiconductor material over the first semiconductor material; and
forming a stack of nanostructures by removing the sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the stack of nanostructures, wherein an uppermost surface of the first semiconductor material is lower than a lower surface of a lowermost nanostructure of the stack of nanostructures in a cross-sectional view.