| CPC H01L 29/7851 (2013.01) [H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure by alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a substrate;
forming an active structure extending in a first direction by removing a portion of the stacked structure and a portion of the substrate;
forming sacrificial gate structures on the substrate, extending in a second direction,
and intersecting the active structure;
forming a recess region by removing a portion of the stacked structure exposed between the sacrificial gate structures;
forming first epitaxial layers of a source/drain region having a first composition such that the first epitaxial layers include first layers on side surfaces of the plurality of channel layers in the recess region and a second layer on a bottom surface of the recess region;
forming a second epitaxial layer of the source/drain region such that the second epitaxial layer has a second composition different from the first composition on the first epitaxial layers to fill the recess region;
forming an interlayer insulating layer covering the source/drain region and filling a gap between the sacrificial gate structures; and
removing the sacrificial gate structures and forming gate structures in regions in which the sacrificial gate structures are removed,
wherein the second epitaxial layer is between the first epitaxial layers in the first direction and is between the first epitaxial layers in a third direction, which is a vertical direction perpendicular to the first direction and the second direction.
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