US 12,132,110 B2
Synaptic transistor with long-term and short-term memory
Dae Hwan Kim, Seoul (KR); Dong Yeon Kang, Seongnam-si (KR); Jun Tae Jang, Bucheon-si (KR); Shin Young Park, Seoul (KR); Hyun Kyu Lee, Suwon-si (KR); Sung Jin Choi, Seoul (KR); Dong Myoung Kim, Seoul (KR); and Wonjung Kim, Seoul (KR)
Assigned to KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION, Seoul (KR)
Filed by KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION, Seoul (KR)
Filed on Aug. 31, 2021, as Appl. No. 17/462,554.
Claims priority of application No. 10-2020-0114325 (KR), filed on Sep. 8, 2020; application No. 10-2020-0114326 (KR), filed on Sep. 8, 2020; and application No. 10-2020-0114327 (KR), filed on Sep. 8, 2020.
Prior Publication US 2022/0077314 A1, Mar. 10, 2022
Int. Cl. H01L 29/786 (2006.01); G06N 3/063 (2023.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01)
CPC H01L 29/7841 (2013.01) [G06N 3/063 (2013.01); H01L 21/02178 (2013.01); H01L 21/02565 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/7883 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A synaptic transistor with long-term and short-term memory characteristics, comprising:
a substrate;
a bottom gate electrode disposed on the substrate;
a first gate insulating layer comprising ions, covering the bottom gate electrode, and disposed on the substrate;
a floating gate electrode disposed on the first gate insulating layer to correspond to the bottom gate electrode;
a second gate insulating layer comprising ions, covering the floating gate electrode, and disposed on the first gate insulating layer;
a channel layer disposed on the second gate insulating layer to correspond to the floating gate electrode; and
source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the second gate insulating layer.