US 12,132,099 B2
LDMOS transistor with implant alignment spacers
Hernan Rueda, Chandler, AZ (US); Rodney Arlan Barksdale, Buda, TX (US); Stephen C. Chew, Dripping Springs, TX (US); Martin Garcia, Buda, TX (US); and Wayne Geoffrey Risner, Austin, TX (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, INC., Austin, TX (US)
Filed on Mar. 27, 2023, as Appl. No. 18/190,452.
Application 18/190,452 is a division of application No. 17/316,091, filed on May 10, 2021, granted, now 11,664,443.
Prior Publication US 2023/0231034 A1, Jul. 20, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66689 (2013.01) [H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/7816 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor comprising:
a gate stack comprising a first nitride layer on a silicon layer, the gate stack separated from a substrate by a first oxide layer;
a polysilicon layer formed from the silicon layer, wherein a second oxide layer is formed on a sidewall of the polysilicon layer;
a drain region that includes a first implant aligned to a first edge formed by the second oxide layer;
a second nitride layer conformingly covering the second oxide layer; and
a nitride etch-stop layer conformingly covering the second nitride layer.