US 12,132,096 B2
Semiconductor device structure with metal gate stack
Xusheng Wu, Hsinchu (TW); Chang-Miao Liu, Hsinchu (TW); and Huiling Shang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 27, 2023, as Appl. No. 18/360,110.
Application 17/135,339 is a division of application No. 16/392,130, filed on Apr. 23, 2019, granted, now 10,879,373, issued on Dec. 29, 2020.
Application 18/360,110 is a continuation of application No. 17/135,339, filed on Dec. 28, 2020, granted, now 11,769,819.
Prior Publication US 2023/0378321 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/82 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/26586 (2013.01); H01L 21/28008 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/4236 (2013.01); H01L 29/49 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a substrate;
a gate stack over the substrate; and
a spacer element over a sidewall of the gate stack, wherein the spacer element is doped with a dopant, the dopant reduces a dielectric constant of the spacer element, the spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack, the spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element, and the first atomic concentration of the dopant is different than the second atomic concentration of the dopant.