US 12,132,092 B2
Backside vias in semiconductor device
Li-Zhen Yu, New Taipei (TW); Huan-Chieh Su, Tianzhong Township (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 13, 2022, as Appl. No. 17/743,992.
Application 17/743,992 is a continuation of application No. 16/984,881, filed on Aug. 4, 2020, granted, now 11,349,004.
Claims priority of provisional application 63/016,377, filed on Apr. 28, 2020.
Prior Publication US 2022/0278213 A1, Sep. 1, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/4238 (2013.01) [H01L 21/76804 (2013.01); H01L 21/823418 (2013.01); H01L 29/0665 (2013.01); H01L 29/4933 (2013.01); H01L 29/6656 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first transistor structure on a semiconductor substrate and a second transistor structure on the semiconductor substrate adjacent the first transistor structure; and
forming a first interconnect structure on a backside of the first transistor structure and the second transistor structure, wherein forming the first interconnect structure comprises:
forming a first contact electrically coupled to a first source/drain region of the first transistor structure; and
forming a second contact electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact, wherein a first surface of the first contact opposite the first source/drain region is coplanar with a second surface of the second contact opposite the second source/drain region.