US 12,132,063 B2
Semiconductor package and method for manufacturing semiconductor package
Masami Suzuki, Kanagawa (JP); and Daisuke Chino, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/612,711
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Apr. 8, 2020, PCT No. PCT/JP2020/015779
§ 371(c)(1), (2) Date Nov. 19, 2021,
PCT Pub. No. WO2020/241068, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. 2019-100901 (JP), filed on May 30, 2019.
Prior Publication US 2022/0271068 A1, Aug. 25, 2022
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/1462 (2013.01) [H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14687 (2013.01); H01L 27/1464 (2013.01); H01L 27/14645 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a pair of substrates including a first substrate and a second substrate;
a semiconductor integrated circuit on the first substrate;
a wiring on the second substrate, wherein the wiring connects the semiconductor integrated circuit to an external terminal; and
a ferromagnetic material on the second substrate, wherein the ferromagnetic material is between the wiring and the semiconductor integrated circuit.