US 12,132,051 B2
Method of manufacturing semiconductor devices and semiconductor devices
Shahaji B. More, Hsinchu (TW); and Chandrashekhar Prakash Savant, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/875,277.
Application 17/875,277 is a division of application No. 17/184,150, filed on Feb. 24, 2021, granted, now 11,955,485.
Application 17/184,150 is a continuation in part of application No. 17/104,019, filed on Nov. 25, 2020, granted, now 11,557,649.
Claims priority of provisional application 63/045,433, filed on Jun. 29, 2020.
Prior Publication US 2022/0375937 A1, Nov. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 29/517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer in a gate space, the gate space being laterally surrounded by one or more insulating layers;
separating the gate dielectric layer into a first gate dielectric layer and a second gate dielectric layer by a trench by:
forming a first mask layer over the gate dielectric layer;
forming a second mask layer over the first mask layer;
patterning the second mask layer;
forming the trench by patterning the first mask layer and the gate dielectric layer; and
removing the patterned second mask layer;
forming one or more work function adjustment material (WFM) layers over the first gate dielectric layer and the second gate dielectric layer; and
forming a body gate electrode layer over the one or more WFM layers,
wherein the trench is filled by a part of the one or more WFM layers.