| CPC H01L 27/088 (2013.01) [H01L 21/762 (2013.01); H01L 21/823412 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 29/66674 (2013.01); H01L 29/7801 (2013.01)] | 15 Claims |
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1. A semiconductor device comprising:
a buried impurity layer disposed in a substrate;
a first gate electrode and a second gate electrode arranged symmetrically with respect to a bulk tap region disposed on a top surface of the substrate;
a first well region disposed below the first and second gate electrodes and the bulk tap region, and arranged symmetrically with respect to the bulk tap region;
a first deep well region disposed below the first well region, arranged symmetrically with respect to the bulk tap region, and surrounded by a first epitaxial layer,
wherein the first deep well region is in direct contact with an upper surface of the buried impurity layer and has a doping concentration lower than a doping concentration of the first well region;
a second deep well region and a third deep well region arranged symmetrically with respect to the first deep well region, the second and third deep well regions each having a conductivity type opposite to the first deep well region and the first well region,
wherein the second deep well region and the third deep well region are in direct contact with the upper surface of the buried impurity layer;
a source region disposed in the first well region;
a first drain region disposed on the second deep well region;
a second drain region disposed on the third deep well region:
silicide layers disposed on the source region, the first drain region, and the second drain region; and
a deep trench isolation region surrounding the silicide layers and the first and second gate electrodes, and
wherein the deep trench isolation region is disposed vertically to pass through the second deep well region and the buried impurity layer.
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