US 12,132,045 B2
Semiconductor capacitor array layout capable of generating parasitic capacitance toward edge of layout
Shih-Hsiung Huang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Jun. 1, 2023, as Appl. No. 18/204,619.
Application 18/204,619 is a division of application No. 17/676,855, filed on Feb. 22, 2022, granted, now 11,810,916.
Claims priority of application No. 110116897 (TW), filed on May 11, 2021.
Prior Publication US 2023/0317721 A1, Oct. 5, 2023
Int. Cl. H01L 27/08 (2006.01)
CPC H01L 27/0805 (2013.01) 7 Claims
OG exemplary drawing
 
1. A semiconductor capacitor array layout capable of generating parasitic capacitance toward an edge of the semiconductor capacitor array layout, the semiconductor capacitor array layout comprising a primary capacitor structure and an outer capacitor structure, wherein:
the primary capacitor structure includes:
a first conductive structure including longitudinal first conductive strips and lateral first conductive strips, wherein the longitudinal first conductive strips are located in a first integrated circuit (IC) layer, and the lateral first conductive strips are located in a second IC layer and coupled to the longitudinal first conductive strips through first vias; and
a second conductive structure including longitudinal second conductive strips and lateral second conductive strips, wherein the longitudinal second conductive strips are located in the first IC layer, the lateral second conductive strips are located in the second IC layer and coupled to the longitudinal second conductive strips through second vias, the longitudinal first conductive strips and the longitudinal second conductive strips are alternatively disposed in the first IC layer, and the lateral first conductive strips and the lateral second conductive strips are alternatively disposed in the second IC layer; and
the outer capacitor structure includes:
a third conductive structure including longitudinal third conductive strips and lateral third conductive strips, wherein the longitudinal third conductive strips are located in the first IC layer, and the lateral third conductive strips are located in the second IC layer and coupled to the longitudinal third conductive strips through third vias; and
a fourth conductive structure including longitudinal fourth conductive strips and lateral fourth conductive strips, wherein the longitudinal fourth conductive strips are located in the first IC layer, the lateral fourth conductive strips are located in the second IC layer, the longitudinal third conductive strips and the longitudinal fourth conductive strips are alternatively disposed in the first IC layer, and the lateral third conductive strips and the lateral fourth conductive strips are alternatively disposed in the second IC layer,
wherein the first conductive structure and the third conductive structure are electrically coupled together and used for transmission of a first voltage; the second conductive structure is used for transmission of a second voltage; the fourth conductive structure is used for transmission of a predetermined voltage or not used for any voltage transmission; the first voltage is different from each of the second voltage and the predetermined voltage; the second voltage is different from the predetermined voltage; and the second conductive structure and the third conductive structure jointly generate the parasitic capacitance.