US 12,132,022 B2
Semiconductor devices and preparation methods thereof
Zengyan Fan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/430,856
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Mar. 8, 2021, PCT No. PCT/CN2021/079567
§ 371(c)(1), (2) Date Aug. 13, 2021,
PCT Pub. No. WO2021/203887, PCT Pub. Date Oct. 14, 2021.
Claims priority of application No. 202010279566.8 (CN), filed on Apr. 10, 2020.
Prior Publication US 2023/0054495 A1, Feb. 23, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 23/3171 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/11019 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13018 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/14517 (2013.01); H01L 2924/35121 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
a passivation layer, arranged on an upper surface of the semiconductor substrate;
a protective layer, arranged on an upper surface of the passivation layer, a dummy opening with a block groove being formed on the protective layer;
a dummy bump, partially located in the dummy opening and closely adhered to the protective layer, wherein a block portion of the dummy bump, located in the block groove, directly adhered to the passivation layer; and
a seed layer, formed on a bottom of the dummy opening by sputtering and located between the dummy bump and the passivation layer.