US 12,132,019 B2
Packaged multi-chip semiconductor devices and methods of fabricating same
Hyuekjae Lee, Hwaseong-si (KR); Jongho Lee, Hwaseong-si (KR); Jihoon Kim, Cheonan-si (KR); Taehun Kim, Asan-si (KR); Sangcheon Park, Hwaseong-si (KR); Jinkyeong Seol, Cheonan-si (KR); and Sanghoon Lee, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 9, 2023, as Appl. No. 18/151,622.
Application 18/151,622 is a continuation of application No. 17/155,657, filed on Jan. 22, 2021, granted, now 11,552,033.
Claims priority of application No. 10-2020-0059328 (KR), filed on May 18, 2020.
Prior Publication US 2023/0163088 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/06 (2013.01) [H01L 21/561 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/92 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08148 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/83099 (2013.01); H01L 2224/8389 (2013.01); H01L 2224/92142 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A packaged semiconductor device, comprising:
a connection structure;
a first semiconductor chip on an upper surface of the connection structure;
a first bond pad on the first semiconductor chip;
a first electrically conductive through substrate via (TSV), which extends through a substrate of the first semiconductor chip and is electrically connected to the first bond pad;
a first bond insulation layer, which extends on the first semiconductor chip and at least partially surrounds the first bond pad;
a second bond pad directly contacting the first bond pad;
a second bond insulation layer at least partially surrounding the second bond pad;
a second semiconductor chip on the second bond pad and the second bond insulation layer, said second semiconductor chip comprising a substrate and a semiconductor device on the lower surface of the substrate; and
a third semiconductor chip arranged beside the second semiconductor chip;
a first molding layer located on the second bond insulation layer and at least partially surrounding the second semiconductor chip and the third semiconductor chip.