US 12,132,018 B2
Transmission circuit, interface circuit, and memory
Feng Lin, Shanghai (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Oct. 25, 2021, as Appl. No. 17/452,235.
Application 17/452,235 is a continuation of application No. PCT/CN2021/101365, filed on Jun. 21, 2021.
Claims priority of application No. 202010873287.4 (CN), filed on Aug. 26, 2020.
Prior Publication US 2022/0068854 A1, Mar. 3, 2022
Int. Cl. H01L 23/00 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); H01L 21/66 (2006.01)
CPC H01L 24/06 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); H01L 22/32 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06515 (2013.01); H01L 2924/1436 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A transmission circuit, comprising:
an upper-layer clock bonding pad, configured to transmit a clock signal;
M upper-layer data bonding pads, configured to transmit data signals;
a lower-layer clock bonding pad, electrically connected with the upper-layer clock bonding pad, wherein an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and
M lower-layer data bonding pads, electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, wherein an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad;
wherein the upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, and the first layer, the dielectric layer and the second layer are all located on a same substrate, M being an integer greater than or equal to 2;
wherein the lower-layer data bonding pads are arranged in two parallel rows, and the lower-layer clock bonding pad is located in one of the two parallel rows; and
wherein part of the upper-layer data bonding pads and the upper-layer clock bonding pad are arranged in a same row, and remaining upper-layer data bonding pads are arranged in a same column around two or more sides of the two parallel rows of the lower-layer data bonding pads and the lower-layer clock bonding pad.