US 12,132,015 B2
Package embedded magnetic inductor structures and manufacturing techniques for 5-50 MHZ SMPS operations
William J. Lambert, Chandler, AZ (US); and Sri Chaitra Jyotsna Chavali, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 28, 2019, as Appl. No. 16/665,682.
Prior Publication US 2021/0125944 A1, Apr. 29, 2021
Int. Cl. H01L 23/64 (2006.01); H01F 27/28 (2006.01); H01F 27/32 (2006.01); H01F 41/04 (2006.01); H01F 41/12 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/49 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/645 (2013.01) [H01F 27/2804 (2013.01); H01F 27/327 (2013.01); H01F 41/041 (2013.01); H01F 41/127 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01F 2027/2809 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19103 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An inductor, comprising:
a substrate layer that surrounds a magnetic layer, wherein the magnetic layer is embedded between the substrate layer, and wherein the magnetic layer has a sidewall;
a dielectric layer that surrounds the substrate layer and the magnetic layer, wherein the dielectric layer fully embeds the substrate layer and the magnetic layer, and wherein the dielectric layer is in contact with the sidewall of the magnetic layer;
a first conductive layer over the dielectric layer;
a second conductive layer below the dielectric layer; and
a plurality of plated-through-hole (PTH) vias in the dielectric layer and the substrate layer, wherein the plurality of PTH vias vertically extend from the first conductive layer to the second conductive layer, wherein the magnetic layer is laterally between the plurality of PTH vias, and wherein each one of the plurality of PTH vias is in contact with the substrate layer.