US 12,132,009 B2
Semiconductor package
Su Chang Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 5, 2023, as Appl. No. 18/143,932.
Application 18/143,932 is a continuation of application No. 17/375,926, filed on Jul. 14, 2021, granted, now 11,646,275.
Application 17/375,926 is a continuation of application No. 16/866,988, filed on May 5, 2020, granted, now 11,088,091, issued on Aug. 10, 2021.
Application 16/866,988 is a continuation of application No. 16/115,851, filed on Aug. 29, 2018, granted, now 10,651,133, issued on May 12, 2020.
Claims priority of application No. 10-2018-0010700 (KR), filed on Jan. 29, 2018.
Prior Publication US 2023/0275036 A1, Aug. 31, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/28 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H01L 23/29 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 23/16 (2013.01); H01L 23/28 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/3142 (2013.01); H01L 23/367 (2013.01); H01L 23/3675 (2013.01); H01L 23/49816 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 23/295 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate having a first surface and a second surface opposing the first surface;
a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads;
a first semiconductor chip disposed on the first surface of the substrate and connected to a first portion of the plurality of first pads;
a second semiconductor chip disposed on the first surface of the substrate spaced apart from the first semiconductor chip, and connected to a second portion of the plurality of first pads, the second semiconductor chip having a side surface facing a side surface of the first semiconductor chip;
an underfill disposed between the first and second semiconductor chips and the first surface of the substrate, and having a first extension portion extended along facing side surfaces of the first and second semiconductor chips in a direction perpendicular to the first surface of the substrate, the first extension portion having an upper end which is lower than upper surfaces of the first and second semiconductor chips and has a concave shape of which a lowermost surface is higher than lower surfaces of the first and second semiconductor chips; and
a sealing material disposed on the first surface of the substrate, and sealing the first and second semiconductor chips, the sealing material having a covering portion extended between the facing side surfaces of the first and second semiconductor chips to be in contact with the first extension portion.