US 12,132,002 B2
Bridge interconnection with layered interconnect structures
Yueli Liu, Gilbert, AZ (US); Qinglei Zhang, Chandler, AZ (US); Amanda E. Schuckman, Scottsdale, AZ (US); and Rui Zhang, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 26, 2023, as Appl. No. 18/139,862.
Application 14/836,906 is a division of application No. 13/903,828, filed on May 28, 2013, granted, now 9,147,663, issued on Sep. 29, 2015.
Application 18/139,862 is a continuation of application No. 17/410,716, filed on Aug. 24, 2021, granted, now 11,694,960.
Application 17/410,716 is a continuation of application No. 16/596,620, filed on Oct. 8, 2019, granted, now 11,133,257, issued on Sep. 28, 2021.
Application 16/596,620 is a continuation of application No. 16/129,577, filed on Sep. 12, 2018, granted, now 10,475,745, issued on Nov. 12, 2019.
Application 16/129,577 is a continuation of application No. 15/478,858, filed on Apr. 4, 2017, granted, now 10,103,103, issued on Oct. 16, 2018.
Application 15/478,858 is a continuation of application No. 14/836,906, filed on Aug. 26, 2015, granted, now 9,640,485, issued on May 2, 2017.
Prior Publication US 2024/0014138 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H05K 1/18 (2006.01); H05K 3/34 (2006.01)
CPC H01L 23/5381 (2013.01) [H01L 23/53238 (2013.01); H01L 23/538 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/09 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/26 (2013.01); H01L 24/27 (2013.01); H01L 24/33 (2013.01); H01L 24/81 (2013.01); H01L 24/82 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H05K 1/185 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/171 (2013.01); H01L 2224/2746 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/33505 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81411 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/81463 (2013.01); H01L 2224/81466 (2013.01); H01L 2224/8147 (2013.01); H01L 2224/81472 (2013.01); H01L 2224/81479 (2013.01); H01L 2224/81481 (2013.01); H01L 2224/81484 (2013.01); H01L 2224/81487 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/0103 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01072 (2013.01); H01L 2924/0496 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10363 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An IC assembly, comprising:
a package substrate having a cavity;
a bridge disposed in the cavity of the package substrate, wherein the bridge comprises a silicon substrate;
a dielectric layer over the bridge;
a first interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the first interconnect piece is disposed extending in and over the dielectric layer, wherein the first interconnect piece comprises copper;
a first layer on the first interconnect piece, wherein the first layer comprises nickel;
a second interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the second interconnect piece is disposed extending in and over the dielectric layer, wherein the second interconnect piece comprises copper;
a second layer on the second interconnect piece, wherein the second layer comprises nickel;
a first interconnect structure disposed in the package substrate, wherein the first interconnect structure is laterally spaced from a first side of the bridge, wherein the first interconnect structure extends through the dielectric layer;
a second interconnect structure disposed in the package substrate, wherein the second interconnect structure is laterally spaced from a second side of the bridge, wherein the second interconnect structure extends through the dielectric layer;
a first die electrically coupled with the first interconnect piece and the first interconnect structure; and
a second die electrically coupled with the second interconnect piece and the second interconnect structure.