US 12,131,998 B2
Integrated circuit, system and method of forming same
Te-Hsin Chiu, Hsinchu (TW); Kam-Tou Sio, Hsinchu (TW); Shih-Wei Peng, Hsinchu (TW); Wei-Cheng Lin, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 10, 2023, as Appl. No. 18/298,172.
Application 18/298,172 is a division of application No. 17/237,530, filed on Apr. 22, 2021, granted, now 11,626,369.
Claims priority of provisional application 63/091,664, filed on Oct. 14, 2020.
Prior Publication US 2023/0245970 A1, Aug. 3, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/823871 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit, the method comprising:
fabricating a set of transistors in a front-side of a substrate;
fabricating a first set of vias in a back-side of the substrate opposite from the front-side, the first set of vias being electrically coupled to the set of transistors;
depositing a first set of conductive structures on the back-side of the substrate on a first level, at least a first structure of the first set of conductive structures being electrically coupled to a first via of the first set of vias;
depositing a second set of conductive structures on the back-side of the substrate on a second level thereby forming a set of power rails, the second level being different from the first level;
fabricating a second set of vias in the back-side of the substrate; and
depositing a third set of conductive structures on the back-side of the substrate on a third level different from the first level and the second level, the second set of vias being electrically coupled to the third set of conductive structures and the first set of conductive structures.