| CPC H01L 23/5283 (2013.01) [H01L 29/42356 (2013.01); H10B 43/27 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a pattern structure;
a stack structure including a plurality of gate layers stacked and spaced apart from each other in a vertical direction in a first region on the pattern structure and extending into a second region on the pattern structure;
a memory vertical structure penetrating through the stack structure in the first region; and
a plurality of gate contact plugs electrically connected to the plurality of gate layers in the second region,
wherein the plurality of gate layers includes a first gate layer,
wherein the plurality of gate contact plugs includes a gate contact plug in contact with and electrically connected to the first gate layer,
wherein a side surface of the gate contact plug includes a first upper bending portion,
wherein a side surface of the memory vertical structure includes a second upper bending portion, and
wherein the first upper bending portion and the second upper bending portion are at a higher level than an uppermost gate layer of the plurality of gate layers.
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