	US 12,131,991 B2
	Self aligned gratings for tight pitch interconnects and methods of fabrication
Manish Chandhok, Beaverton, OR (US); Leonard Guler, Hillsboro, OR (US); Paul Nyhus, Portland, OR (US); Gobind Bisht, Portland, OR (US); Jonathan Laib, Portland, OR (US); David Shykind, Buxton, OR (US); Gurpreet Singh, Portland, OR (US); Eungnak Han, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); Charles Wallace, Portland, OR (US); and Jinnie Aloysius, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 14, 2022, as Appl. No. 17/671,543.
Application 17/671,543 is a continuation of application No. 16/562,346, filed on Sep. 5, 2019, granted, now 11,251,117.
Prior Publication US 2022/0173034 A1, Jun. 2, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)

CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76885 (2013.01); H01L 23/5283 (2013.01); H01L 29/41725 (2013.01); H01L 29/4232 (2013.01)]

20 Claims

1. A method of fabricating an integrated circuit interconnect structure, the method comprising:

forming first and second parallel lines of conductive material, each line extending in a first direction with a first dielectric therebetween;

forming a stack structure over the first dielectric, the stack structure comprising a second dielectric and a third dielectric;

forming a fourth dielectric over the first and second lines;

patterning an opening in the third dielectric and extending in a second direction, orthogonal to the first direction, wherein the opening exposes a portion of the fourth dielectric;

forming a fifth dielectric in the opening and on the exposed portion of the fourth dielectric;

exposing a portion of each of the first and second lines by etching the fourth dielectric where not masked by the fifth dielectric; and

forming a conductive feature on the exposed portion of the first and second lines.