US 12,131,990 B2
Semiconductor structure with a contact to source/drain layers and fabrication method thereof
Fei Zhou, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on May 21, 2021, as Appl. No. 17/326,846.
Claims priority of application No. 202010581157.3 (CN), filed on Jun. 23, 2020.
Prior Publication US 2021/0398901 A1, Dec. 23, 2021
Int. Cl. H01L 23/522 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76877 (2013.01); H01L 21/76883 (2013.01); H01L 21/76897 (2013.01); H01L 29/41775 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/28518 (2013.01); H01L 23/53209 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 29/456 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a plurality of discrete fins on the substrate;
a gate structure, on the substrate and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins;
a plurality of doped source/drain layers, in the plurality of discrete fins and at both sides of the gate structure;
a contact layer covering entire top surfaces of the plurality of doped source/drain layers;
a conductive layer, formed at one or two sides of the gate structure, covering an entire top surface of the contact layer, and connecting multiple doped source/drain layers of the plurality of doped source/drain layers and with a top surface lower than a top surface of the gate structure, a bottom surface of the conductive layer being higher than a bottom surface of the gate structure at the top surfaces of the plurality of discrete fins, and being higher than the top surfaces of the plurality of doped source/drain layers; and
a conductive plug, on the conductive layer and in contact with a portion of the top surface of the conductive layer.
 
6. A method for forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of discrete fins on the substrate;
forming a gate structure, on the substrate and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins;
forming a plurality of doped source/drain layers in the plurality of fins and at both sides of the gate structure;
forming a contact layer on the plurality of doped source/drain layers, the contact layer covering entire top surfaces of the plurality of doped source/drain layers;
forming a conductive layer at one or two sides of the gate structure, wherein the conductive layer covers an entire top surface of the contact layer, and is connected to multiple doped source/drain layers of the plurality of doped source/drain layers and a top surface of the conductive layer is lower than a top surface of the gate structure, a bottom surface of the conductive layer being higher than a bottom surface of the gate structure at the top surfaces of the plurality of discrete fins, and being higher than the top surfaces of the plurality of doped source/drain layers; and
forming a conductive plug, on the conductive layer and in contact with a portion of the top surface of the conductive layer.
 
19. A method for forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of discrete fins on the substrate;
forming a gate structure, on the substrate and across the plurality of fins by covering portions of sidewall surfaces and top surfaces of the plurality of fins;
forming a plurality of doped source/drain layers in the plurality of fins and at both sides of the gate structure;
forming a first dielectric layer, on the substrate and covering sidewall surfaces of the plurality of doped source/drain layers and sidewall surfaces of the gate structure;
forming a second dielectric layer on the first dielectric layer and the gate structure;
forming a conductive layer at one or two sides of the gate structure, wherein the conductive layer is connected to multiple doped source/drain layers of the plurality of doped source/drain layers and a top surface of the conductive layer is lower than a top surface of the gate structure, a bottom surface of the conductive layer being higher than a bottom surface of the gate structure, and forming the conductive layer including:
forming a first dielectric layer opening in the first dielectric layer and the second dielectric layer to expose the plurality of doped source/drain layers and the gate structure;
forming an initial conductive layer on the plurality of doped source/drain layers and the gate structure to fill the first dielectric layer opening; and
etching the initial conductive layer to form the conductive layer with the top surface lower than the top surface of the gate structure; and
forming a conductive plug, on the conductive layer and in contact with a portion of the top surface of the conductive layer.