US 12,131,981 B2
Power module package baseplate with step recess design
Yushuang Yao, Shenzhen (CN); and Vemmond Jeng Hung Ng, Senawang (MY)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Jul. 24, 2023, as Appl. No. 18/357,931.
Application 18/357,931 is a continuation of application No. 16/949,869, filed on Nov. 18, 2020, granted, now 11,735,504.
Prior Publication US 2023/0369176 A1, Nov. 16, 2023
Int. Cl. H01L 23/492 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/4924 (2013.01) [H01L 21/4871 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method for a semiconductor package comprising:
performing a material removal operation on a baseplate at a region of a surface of the baseplate to produce a recess in the baseplate, the recess including a recess base, a first sidewall, and a second sidewall;
receiving a substrate, the substrate including:
a dielectric layer;
a first metal layer disposed on a first surface of the dielectric layer; and
a second metal layer disposed on a second surface of the dielectric layer; and
attaching the substrate to a surface of the recess base of the recess via a conductive-bonding component, the surface of the recess base being contiguous with the first sidewall.