US 12,131,966 B2
Semiconductor wafer and method of manufacturing semiconductor apparatus
Fuyuma Ito, Yokkaichi (JP); Yasuhito Yoshimizu, Yokkaichi (JP); Nobuhito Kuge, Yokkaichi (JP); Yui Kagi, Yokkaichi (JP); Susumu Obata, Yokohama (JP); Keiichiro Matsuo, Yokohama (JP); and Mitsuo Sano, Kamakura (JP)
Assigned to KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and Kioxia Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and Kioxia Corporation, Tokyo (JP)
Filed on Sep. 7, 2021, as Appl. No. 17/467,839.
Application 17/467,839 is a continuation of application No. PCT/JP2020/010406, filed on Mar. 10, 2020.
Claims priority of application No. 2019-052867 (JP), filed on Mar. 20, 2019.
Prior Publication US 2021/0407867 A1, Dec. 30, 2021
Int. Cl. H01L 21/66 (2006.01); C30B 25/18 (2006.01); H01L 21/02 (2006.01); H10B 43/27 (2023.01)
CPC H01L 22/30 (2013.01) [C30B 25/186 (2013.01); H01L 21/02002 (2013.01); H01L 21/02005 (2013.01); H01L 22/34 (2013.01); H10B 43/27 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A semiconductor wafer, comprising:
a surface having at least one recess including an inner wall surface and a bottom surface, the inner wall surface and the bottom surface being exposed, wherein:
the at least one recess includes a first recess and a second recess;
the first recess extends along a first direction of the surface;
the second recess extends along a second direction intersecting with the first direction on the surface;
each of the first and second recesses is surrounded by the corresponding inner wall surface; and
the surface further has a porous region.