US 12,131,950 B2
Method for fabricating a semiconductor device
Jae Man Yoon, Gyeonggi-do (KR); Jin Hwan Jeon, Gyeonggi-do (KR); Tae Kyun Kim, Gyeonggi-do (KR); Jung Woo Park, Gyeonggi-do (KR); Su Ock Chung, Gyeonggi-do (KR); and Jae Won Ha, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 18, 2023, as Appl. No. 18/542,779.
Application 18/542,779 is a division of application No. 17/719,990, filed on Apr. 13, 2022, granted, now 11,895,828.
Claims priority of application No. 10-2021-0130237 (KR), filed on Sep. 30, 2021.
Prior Publication US 2024/0121948 A1, Apr. 11, 2024
Int. Cl. H01L 21/76 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/76897 (2013.01) [H01L 21/76831 (2013.01); H10B 12/0335 (2023.02); H10B 12/482 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device comprising:
forming a device isolation layer defining a plurality of active regions in a substrate;
forming a conductive layer over the device isolation layer and the active regions;
etching the conductive layer, and forming conductive lines extending in a first direction and trenches between the conductive lines;
forming a spacer on sidewalls of the trenches;
forming hole-shaped recess portions by etching active regions disposed below the trenches so that the active regions are aligned with the spacer,
forming lower-level plugs filling the hole-shaped recess portions;
forming buried bit lines over the lower-level plugs; and
forming upper-level plugs between the buried bit lines by etching the conductive lines along a second direction, the second direction intersecting the first direction.