US 12,131,800 B2
Physically unclonable cell using dual-interlocking and error correction techniques
Mahmut Ersin Sinangil, Los Altos, CA (US); Sudhir Shrikantha Kudva, Dublin, CA (US); Nikola Nedovic, San Jose, CA (US); and Carl Thomas Gray, Apex, NC (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Nov. 16, 2022, as Appl. No. 18/056,158.
Prior Publication US 2024/0161800 A1, May 16, 2024
Int. Cl. G11C 7/24 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01)
CPC G11C 7/24 (2013.01) [G11C 7/1063 (2013.01); G11C 7/20 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A circuit comprising:
at least one power supply; and
a Physically Unclonable Function (PUF) cell comprising a dual-interlocked inverter arrangement configured with switches operable to bypass a dual-interlock of the inverter arrangement.