US 12,131,799 B2
Trim/test interface for devices with low pin count or analog or no-connect pins
Rajat Chauhan, Karnataka (IN); Divya Kaur, Delhi (IN); and Rishav Gupta, Punjab (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 31, 2023, as Appl. No. 18/203,806.
Application 18/203,806 is a continuation of application No. 17/537,872, filed on Nov. 30, 2021, granted, now 11,705,169.
Claims priority of application No. 202041056137 (IN), filed on Dec. 23, 2020.
Prior Publication US 2023/0343375 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); H03K 19/007 (2006.01)
CPC G11C 7/1084 (2013.01) [H03K 19/007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a first terminal of one or more terminals of the IC configured to receive a first signal associated with a first mode and a second signal associated with a second mode, wherein the second mode configures the IC device into a test mode configured to receive test inputs on the one or more terminals of the IC and to provide test outputs on the one or more terminals of the IC;
and
a test interface including:
a logic circuit configured to transition the IC device from the first mode to the second mode; and
an always-on complementary metal-oxide-semiconductor (CMOS) input buffer coupled at a first end to the first terminal and at a second end to an input of the logic circuit.