US 12,131,798 B2
Non-volatile memory device for detecting defects of bit lines and word lines
Junyoung Ko, Suwon-si (KR); Sangwan Nam, Suwon-si (KR); Youse Kim, Suwon-si (KR); and Heewon Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 24, 2022, as Appl. No. 17/972,300.
Claims priority of application No. 10-2021-0154255 (KR), filed on Nov. 10, 2021; and application No. 10-2022-0059814 (KR), filed on May 16, 2022.
Prior Publication US 2023/0144141 A1, May 11, 2023
Int. Cl. G11C 7/10 (2006.01); G06F 11/10 (2006.01)
CPC G11C 7/1057 (2013.01) [G06F 11/1076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a memory cell array comprising a plurality of cell strings, each comprising a plurality of memory cells respectively connected to a plurality of word lines;
a page buffer circuit comprising a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines, wherein a first page buffer from among the plurality of page buffers is connected to a first cell string from among the plurality of cell strings through a first bit line from among the plurality of bit lines;
a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the plurality of word lines and the first bit line; and
a defect detection circuit configured to detect defects of the plurality of word lines based on a result of the pre-sensing operation and a result of the post-sensing operation.