US 12,131,785 B2
Weak erase pulse
Chao Zhang, Milpitas, CA (US); Krishna Parat, Palo Alto, CA (US); Richard Fastow, Cupertino, CA (US); Ricardo Basco, Santa Clara, CA (US); Xin Sun, Fremont, CA (US); Heonwook Kim, Santa Clara, CA (US); and Zhan Liu, Santa Clara, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Jun. 1, 2022, as Appl. No. 17/829,837.
Prior Publication US 2022/0293189 A1, Sep. 15, 2022
Int. Cl. G11C 16/08 (2006.01); G11C 7/04 (2006.01); G11C 16/16 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 7/04 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/349 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory chip controller comprising:
one or more substrates, and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
bias a word line of a block in NAND memory to a first voltage level,
bias a source-side select gate and a drain-side select gate of the block to a second voltage level, and
issue a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse.