US 12,131,781 B2
Semiconductor devices and data storage systems including the same
Jaeduk Lee, Seongnam-si (KR); Kinam Kim, Seoul (KR); and Sujin Ahn, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 8, 2022, as Appl. No. 17/689,005.
Claims priority of application No. 10-2021-0032831 (KR), filed on Mar. 12, 2021.
Prior Publication US 2022/0293180 A1, Sep. 15, 2022
Int. Cl. G11C 16/04 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC G11C 16/0483 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first separation structure and a second separation structure parallel to each other on a lower structure;
a block between the first separation structure and the second separation structure and on the lower structure; and
a plurality of bit lines on the first and second separation structures and on the block,
wherein
the block includes a plurality of strings,
the plurality of bit lines include a first bit line that is electrically connected to a first string and a second string of the plurality of strings,
each of the plurality of strings includes a lower select transistor, a plurality of memory cell transistors, and a plurality of upper select transistors, the plurality of memory cell transistors are between the lower select transistor and the plurality of upper select transistors, and the lower select transistor, the plurality of memory cell transistors, and the plurality of upper select transistors are connected in series,
the plurality of upper select transistors in each of the plurality of strings include a first upper select transistor and a second upper select transistor that is between the first upper select transistor and the plurality of memory cell transistors,
the first upper select transistor of the first string and the first upper select transistor of the second string respectively include first and second portions of a single first upper select gate electrode,
the lower select transistor of the first string includes a first lower select gate electrode, and
the lower select transistor of the second string includes a second lower select gate electrode having a surface that is coplanar with a surface of the first lower select gate electrode and is electrically isolated from the first lower select gate electrode.