US 12,131,778 B2
Triggering of stronger write pulses in a memory device based on prior read operations
Zhongyuan Lu, Boise, ID (US); and Robert John Gleixner, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,988.
Prior Publication US 2024/0071491 A1, Feb. 29, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0033 (2013.01); G11C 13/0035 (2013.01); G11C 13/004 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A system comprising:
a memory array including memory cells;
memory configured to store a record associated with prior read operations for the memory cells; and
a controller configured to:
apply pulses to the memory cells when performing read and write operations, wherein for the write operations the pulses include at least one first write pulse, and at least one second write pulse of a greater magnitude than the first write pulse;
perform at least one read operation on at least one first memory cell of the memory array;
in response to performing the read operation, add a first entry associated with the first memory cell to the record;
select, for performing a write operation on the first memory cell, a write pulse based on the record stored in the memory, wherein the selecting comprises determining that the first entry is in the record, and in response to determining that the first entry is in the record, selecting the second write pulse; and
apply the second write pulse to the first memory cell for performing the write operation.