US 12,131,776 B2
Non-volatile memory based compute-in-memory cell
Zheng-Jun Lin, Taichung (TW); Chin-I Su, Hsinchu (TW); Chung-Cheng Chou, Hsinchu (TW); and Chia-Fu Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 15, 2022, as Appl. No. 17/695,578.
Claims priority of provisional application 63/282,768, filed on Nov. 24, 2021.
Prior Publication US 2023/0162785 A1, May 25, 2023
Int. Cl. G11C 14/00 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H03K 19/20 (2006.01); G11C 13/00 (2006.01); H03K 19/21 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); G11C 14/009 (2013.01); H03K 19/20 (2013.01); G11C 13/0026 (2013.01); H03K 19/21 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a static random-access memory including:
two cross-coupled inverters having a first inverter output connected to a second inverter input, and a second inverter output connected to a first inverter input;
a first access transistor having a first drain/source region connected to a bit line or a bit line bar, a second drain/source region, and a first gate connected to a first word line; and
a second access transistor having a third drain/source region connected to another one of the bit line or the bit line bar, a fourth drain/source region, and a second gate connected to a second word line:
one or more logic gates electrically coupled to the static random-access memory; and
a non-volatile memory having a first end directly connected to the second drain/source region of the first access transistor and a second end directly connected to the first inverter output and the second inverter input and configured to store data and recall the data using the static random-access memory,
wherein to initialize a recall operation to recall the data one of the bit line and the bit line bar is at a low voltage and another one of the bit line and the bit line bar is at a high voltage and the first access transistor and the second access transistor are biased on, and to determine a state of the non-volatile memory the one of the bit line and the bit line bar is at the high voltage and one of the first access transistor and the second access transistor is biased on.