US 12,131,775 B2
Keeper-free volatile memory system
Lalit Gupta, Fremont, CA (US); Stefan P Sywyk, San Jose, CA (US); Andreas Jon Gotterba, Santa Clara, CA (US); and Jesse Wang, Santa Clara, CA (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Feb. 23, 2022, as Appl. No. 17/678,799.
Prior Publication US 2023/0267992 A1, Aug. 24, 2023
Int. Cl. G11C 11/412 (2006.01)
CPC G11C 11/4125 (2013.01) 16 Claims
OG exemplary drawing
 
1. A circuit comprising:
a plurality of bit-storing cells each comprising an output transistor;
the output transistors forming a NOR gate with separate inputs from each of the plurality of bit-storing cells; and
logic to sustain a high binary voltage level on an output of the NOR gate on condition that (a) a read signal is applied to the plurality of bit-storing cells, and (b) a value stored in any of the bit-storing cells satisfies the high binary voltage level.