US 12,131,774 B2
Vertical memory device with a double word line structure
Seung-Hwan Kim, Seoul (KR); Su-Ock Chung, Seoul (KR); and Seon-Yong Cha, Chungcheongbuk-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 18, 2022, as Appl. No. 17/968,082.
Application 17/968,082 is a continuation of application No. 16/728,174, filed on Dec. 27, 2019, granted, now 11,501,827.
Claims priority of application No. 10-2019-0024083 (KR), filed on Feb. 28, 2019.
Prior Publication US 2023/0045324 A1, Feb. 9, 2023
Int. Cl. G11C 11/4097 (2006.01); G11C 7/18 (2006.01); G11C 11/401 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4097 (2013.01) [G11C 7/18 (2013.01); G11C 11/401 (2013.01); H10B 12/30 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A memory device comprising:
a substrate;
a vertical conductive line oriented vertically over the substrate;
an active layer oriented laterally from the vertical conductive line;
a pair of line-shaped conductive lines disposed over the active layer;
a first node electrically connected to the active layer;
a second node over the first node; and
a dielectric material disposed between the first node and the second node,
wherein the pair of line-shaped conductive lines comprises:
a line-shaped lower conductive line disposed over a lower surface of the active layer; and
a line-shaped upper conductive line disposed over an upper surface of the active layer,
wherein the active layer includes:
a first source/drain region coupled to the vertical conductive line;
a second source/drain region coupled to the first node; and
a channel between the first source/drain region and a second source/drain region, and
the first source/drain region, the channel, and the second source/drain region are positioned in a lateral arrangement parallel to the substrate.