US 12,131,767 B2
Apparatuses and methods for generating refresh addresses
Hidekazu Noguchi, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 6, 2022, as Appl. No. 17/929,981.
Application 17/929,981 is a division of application No. 17/093,334, filed on Nov. 9, 2020, granted, now 11,468,937.
Prior Publication US 2023/0005525 A1, Jan. 5, 2023
Int. Cl. G11C 11/406 (2006.01)
CPC G11C 11/40611 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a scrambler circuit configured to:
provide a plurality of least significant bits of a victim row address corresponding to a victim row having a spatial relationship to an aggressor row, the spatial relationship indicated by a control signal, wherein circuitry is used to generate all of the plurality of least significant bits of the victim row address regardless of the spatial relationship indicated by the control signal; and
provide a carry bit based, at least in part, on the control signal; and
a plurality of row hammer count circuits configured to provide a corresponding plurality of most significant bits of the victim row address based, at least in part, on the carry bit.